To allow 32-nm generation high-k metal gate stacks using a single metal, instead of the two different metals required previously for CMOS, semiconductor manufacturing equipment maker ASM America Inc, ...

NEC Corporation and NEC Electronics Corporation announced the development of a transistor featuring a new gate stack structure using a Hf-based high-k dielectric (*1) and a metal gate electrode (*2), ...

To enable EUV in mass production fabs, IC makers must get their hands on defect-free photomasks. Today’s EUV masks have 1 defect per cm^2 at 18-nm. The ultimate goal is to devise EUV masks with 0.003 ...

Applied Materials has launched a system for creating the critical gate dielectric structures in 22nm logic chips. According to the technology specialist, the Applied Centura integrated gate stack ...

Artificial intelligence (AI) has become the workload that defines today’s semiconductor scaling. Whether in hyperscale data centers training foundation models or at the network edge executing ...

Seoul National University’s College of Engineering announced that a research team led by Professor Chul-Ho Lee from the Department of Electrical and Computer Engineering has outlined a comprehensive ...