SINGAPORE--A new consortium has been established to advance the country's next-generation 300mm wafer manufacturing capabilities, by focusing on a technology for three-dimensional integrated circuits ...

Wafer-to-wafer bonding is an essential process step to enable 3D devices such as stacked DRAM, memory-on-logic and future CMOS image sensors. At the same time, minimizing the dimensions of TSVs, which ...

Via reveal, or post-TSV processing occurs after the through silicon vias (TSVs) are formed. The wafer is then temporarily bonded, face down, onto a carrier and ground typically to within 5-10 ...

UnitySC continues to innovate its inspection and metrology products to deliver solutions that address the most advanced needs across semiconductor manufacturing processes. GRENOBLE, France, July 9, ...

January 21, 2013. Imec and PVA Tepla have presented results regarding the detection of TSV voids in 3-D stacked IC technology. After having applied scanning acoustic microscopy (SAM) to temporary ...

The AI trend has fueled the high-bandwidth memory (HBM) business opportunities, which in turn has brought attention to related equipment supplier Hanmi Semiconductor. Recently, to expand its ...

SANTA CLARA, Calif.--(BUSINESS WIRE)--The international EMC-3D semiconductor equipment and materials consortium today announced that Applied Materials, Inc. (Nasdaq:AMAT) has joined the organization.

When it comes to making though-silicon vias, there are no clear lines of delineation about the roles of design houses, fab facilities, and packaging houses. Yet all of these entities face a host of ...

Veteran semiconductor equipment distributor Spirox has successfully entered the advanced packaging supply chain in the second ...

Unpatterned wafer inspection, which has flown well under the radar for most of the semiconductor industry, is becoming more critical amid the need to find defects earlier in the manufacturing process ...