EDN

Trigate and high-kstack up vs. planar

Austin, Texas — Intel Corp. researchers will present a vertical triple-gate structure combined with a high-k oxide and metal electrode gate stack at the 2006 Symposium on VLSI Technology, which kicks ...
sciencex

Towards a process flow for monolithic CFET transistor architectures

—The development of a process flow capable of demonstrating functionality of a monolithic complementary FET (CFET) transistor architecture is complex due to the need to vertically separate nMOS and ...
Nanowerk

CMOS Technology Explained

Complementary Metal-Oxide-Semiconductor (CMOS) technology is a vital part of modern electronics, used in designing and manufacturing integrated circuits (ICs) that power many digital devices. CMOS ...
TechRepublic

Intel’s 45nm CMOS Technology Performance Parameters in VLSI Design

The trend of CMOS technology improvement continues to be driven by the need to integrate more functions within a given silicon area. In this paper, the authors describe Intel’s 45nm technology ...
NextBigFuture

BREAKTHROUGH CMOS N-Type Diamond Transistors

Diamond CMOS needs symmetrical doping control like we have for semiconductor silicon and diamond n-MOS is needed. The n-channel diamond MOSFETs are demonstrated. This work will enable the development ...
EDN

Models for high-voltage transistors in a standard CMOS process

Designers of electronics and communications systems are constantly faced with the challenge of integrating greater functionality on less silicon area. Many of the system blocks – such as power ...